Hdl_plugin is a project mainly written in Vim Script, it's free.
Generate vhdl/verilog testbench file for vhdl files.
This is a mirror of http://www.vim.org/scripts/script.php?script_id=3371
" hdl_plugin is a plugin that enables you to fast instant and generate a testbench file. " it can help you to compile by modelsim convenient. "
" main function: " Add a menu for vim: " create a library " Compile file " Add File Header " Add Content " Process " Module/Entity " Vhdl Component:Creat a window to display the Component information,and add these to clipboard " Verilog Instant : Fast instant for verilog.Also add to clipboard " Vhdl Testbench :Generate a vhdl testbench file " Verilog Testbench :Generate a verilog testbench file
" view details:http://www.cnblogs.com/ifys/archive/2010/11/20/1882673.html# " e-mail: [email protected] " Welcome to post your suggestions to me.