Vlsi681spring09 is a project mainly written in VERILOG and VHDL, it's free.
Class Project for 681 VLSI System Design Course at The University of Cincinnati, Spring 2009
To get started working on the project, you will probably want to set up a few options for using git on your system. Here are some commands that will set some common options for you: (Obviously, you will want to change some of these to reflect your information)
git config --global user.name 'Greg Mefford' git config --global user.email '[email protected]'
There are tons of other options that you can also set. Try searching the Internet for .gitconfig to see some other people's examples.
Getting Started:
That should create an entry in the repository for you change, but right now, it is only in your local repository on your machine. To get it into the public github repository, you need to push it there.
Once we've decided that your change is something we want to put into the "master" branch of the project, you can do so like this:
If other people have made changes, you will need to do the following to update your local repository and see the changes: